The present invention relates to a method of using a buffer with a tri-state controller to output data successively from a plurality of different chips in a bus interface such as a CPU bus, and particularly to a proposal of a method of saving a bus clock cycle at a transition point, that is, at the time when a control for the bus moves from one chip to another.
When a bus interface is configured by a conventional buffer with a tri-state controller, a transient period or state must be created at the transition point of the bus, that is, at the time when other chips come to be controlled. When data is output from two chips in a transient period, it is an unavoidable possibility that a bus is simultaneously driven by the two chips, one having been driving the bus and the other assuming the drive of the bus. Particularly when the two chips output different signal levels including a high level (hereinafter referred to as “H”) and a low level (hereinafter referred to as “L”), a through current flows between the two chips, and an input/output (hereinafter, referred to I/O) cell having a buffer is broken down. For example, when one chip outputs a write data signal and the other chip outputs a read data signal, such a situation may occur.
To make a transient period for preventing the breakdown of the I/O cell due to the through current, current practice is for main circuits synchronized with clocks to prepare a high impedance (hereinafter, referred to as Hi-Z) state for one clock, as shown in FIG. 4, when a bus is switched, for example from a data write operation to a data read operation. This is a large obstacle in circumstances where a bus including a CPU-memory bus is a main factor in determining the performance of a system.
The transient period for one clock can be solved by using an open drain buffer that can set a signal level to only two states of “L” and “H” which is created by pull-up. However, the open drain buffer has problems in that it consumes a large amount of current in the “L” state and it is difficult to realize a high speed operation of the open drain buffer. Accordingly, adoption of the open drain buffer requires circumspection at the present time.
Since it has been impossible to avoid waste equivalent to one clock cycle in switching the bus, there has been a limitation to improvement in the usability of the bus itself. Particularly, in the conventional case, in a bus transaction showing beats of the small number, the problem can be serious because of a sharp decrease in an efficiency of the bus. Specifically, when an access to data is made randomly, the bus efficiency is very low, and this is a large factor to lower CPU performance.